Asynchronous Interface Speci cation, Analysis and Synthesis

Interfaces, by nature, are often asynchronous since they serve for connecting multiple distributed modules/agents without common clock. However, the most recent developments in the theory of asynchronous design in the areas of speci cations, models, analysis, veri cation, synthesis, technology mapping, timing optimization and performance analysis are not widely known and rarely accepted by industry. The goal of this tutorial is to ll this gap and to present an overview of one popular systematic design methodology for design of asynchronous interface controllers. This methodology is based on using Petri nets (PN) a formal model that, from the engineering standpoint, is a formalization of timing diagrams (waveforms) and from the system designer standpoint is a concurrent state machine, in which local components can perform independent or interdependent concurrent actions, changing their local states asynchronously. We will introduce this model informally based on a simple example: a VME-bus controller serving reads from a device to a bus and writes from the bus into the device. 1 Speci cation with Petri Nets 1.1 From timing diagrams to Petri Nets Figure 1 depicts the interface of a device with a VME bus. The behavior of the controller is as follows: a request to read from or write into the device is received by one of the signals DSr or DSw respectively. In a read cycle, a request to read is done through signal LDS. When the device has the data ready (LDTACK), the controller must open the transceiver to transfer data to the bus (signal D). In the write cycle, data is rst transferred to the device. Next, a request to write is done (LDS). Once the device acknowledges the reception of the data (LDTACK) the transceiver must be closed to isolate the device from the bus. Each transaction must be completed by a return-to-zero of all interface signals, seeking for a maximum parallelism between the bus and the device operations. Figure 2 shows a timing diagram of the Work partially supported by ACiD-WG (Esprit 21949) and CICYT TIC 95-0419 DSr